In this talk, we introduce the convergence equivalence condition for parallel orderings in the context of IC(0) preconditioning. Based on the condition, we propose a new parallel ordering method to vectorize and parallelize IC(0) preconditioning, which is called hierarchical block multi-color (HBMC) ordering. The parallel forward and backward substitutions can be vectorized while preserving the advantages of block multi-color ordering, that is, fast convergence and fewer thread synchronizations. Numerical tests were conducted using seven test matrices from the SuiteSparse matrix collection on three types of computational nodes (Intel Xeon Skylake, Broadwell, and Xeon Phi processors). The numerical results indicate that HBMC ordering outperforms the conventional block and nodal multi-color ordering methods. HBMC ordering attains the best result among three parallel ordering methods in 18 out of 21 test cases.