We consider the emergence of so-called “smart” network interface cards, or smartNICs, for high-performance computing systems, focusing on the class of such platforms where the on-NIC “smarts” are supplied by general-purpose multicore processors (in contrast to ASICs or FPGAs). This class has been rebranded by at least one vendor as that of data processing units, or DPUs. Given DPUs, how should one redesign HPC algorithms and software to exploit them? This talk describes our ongoing work to try to answer this question, using mini-applications from computational science and engineering, including molecular dynamics, adaptive mesh refinement, and communication-avoiding (time-tiled) stencil computations as case studies.
This work is led by Sara Karamati, a Ph.D. student at Georgia Tech, and joint with Jeffrey Young (also GT) and colleagues at Sandia National Laboratories.